Invention Grant
- Patent Title: Interconnect congestion reduction for memory-mapped peripherals
- Patent Title (中): 内存映射外围设备的互连拥塞减少
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Application No.: US13455744Application Date: 2012-04-25
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Publication No.: US08667196B2Publication Date: 2014-03-04
- Inventor: Srinivasa Rao Kothamasu , Debjit Roy Choudhury , Dharmesh Kishor Tirthdasani , Sajith Kizhakke Kalathil Achuthan Kutty , Jean Jacob
- Applicant: Srinivasa Rao Kothamasu , Debjit Roy Choudhury , Dharmesh Kishor Tirthdasani , Sajith Kizhakke Kalathil Achuthan Kutty , Jean Jacob
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Otterstedt, Ellenbogen & Kammer, LLP
- Main IPC: G06F13/00
- IPC: G06F13/00

Abstract:
A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.
Public/Granted literature
- US20130290582A1 Interconnect Congestion Reduction for Memory-Mapped Peripherals Public/Granted day:2013-10-31
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