According to one implementation, the slave identifier bits are tested recursively in groups of p bits. For these p bits, each slave will recognize, in its p corresponding identifier bits, one combination out of the 2p possible combinations. The slaves respond simultaneously (20) over the bus, for example an I2C bus, to a request from the master. The response is given by outputting a series of “1” bits in which each slave inserts a “0”, which is, for example, the priority logic value on the bus, the position of the “0” in the series of “1” bits being dependent on the binary value of the combination recognized by the slave in the group of p bits of its identifier. The master progressively determines on the fly, based on the bits of the frame received, the values of bits of these digital information items.