A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.