Invention Grant
US08664987B2 Filtering circuit, phase identity determination circuit and delay locked loop
有权
滤波电路，相位识别确定电路和延迟锁定环
- Patent Title: Filtering circuit, phase identity determination circuit and delay locked loop
- Patent Title (中): 滤波电路，相位识别确定电路和延迟锁定环
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Application No.: US13607234Application Date: 2012-09-07
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Publication No.: US08664987B2Publication Date: 2014-03-04
- Inventor: Dae-Han Kwon , Yong-Ju Kim , Taek-Sang Song
- Applicant: Dae-Han Kwon , Yong-Ju Kim , Taek-Sang Song
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2011-0140494 20111222
- Main IPC: H03K5/00
- IPC: H03K5/00
Abstract:
A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
Public/Granted literature
- US20130162311A1 FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP Public/Granted day:2013-06-27
Information query
