Invention Grant
US08664972B2 Memory control circuit, memory control method, and integrated circuit
有权
存储器控制电路，存储器控制方法和集成电路
- Patent Title: Memory control circuit, memory control method, and integrated circuit
- Patent Title (中): 存储器控制电路，存储器控制方法和集成电路
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Application No.: US13294107Application Date: 2011-11-10
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Publication No.: US08664972B2Publication Date: 2014-03-04
- Inventor: Kohei Murayama , Takeshi Suzuki
- Applicant: Kohei Murayama , Takeshi Suzuki
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2006-284142 20061018
- Main IPC: H03K17/16
- IPC: H03K17/16
Abstract:
Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.
Public/Granted literature
- US20120060003A1 MEMORY CONTROL CIRCUIT, MEMORY CONTROL METHOD, AND INTEGRATED CIRCUIT Public/Granted day:2012-03-08
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