Invention Grant
- Patent Title: Multilayer interconnect structure and method for integrated circuits
- Patent Title (中): 集成电路的多层互连结构和方法
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Application No.: US13096898Application Date: 2011-04-28
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Publication No.: US08664113B2Publication Date: 2014-03-04
- Inventor: Ryoung-Han Kim
- Applicant: Ryoung-Han Kim
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/4763
- IPC: H01L21/4763
Abstract:
A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.
Public/Granted literature
- US20120273958A1 MULTILAYER INTERCONNECT STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS Public/Granted day:2012-11-01
Information query
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