Invention Grant
- Patent Title: MOS transistor, manufacturing method thereof, and semiconductor device
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Application No.: US13761326Application Date: 2013-02-07
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Publication No.: US08664074B2Publication Date: 2014-03-04
- Inventor: Sergey Pidin
- Applicant: Fujitsu Semiconductor Limited
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2010-142936 20100623
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode.
Public/Granted literature
- US08703569B2 MOS transistor, manufacturing method thereof, and semiconductor device Public/Granted day:2014-04-22
Information query
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