Invention Grant
- Patent Title: Method for forming semiconductor structure
- Patent Title (中): 半导体结构形成方法
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Application No.: US13381014Application Date: 2011-04-18
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Publication No.: US08664054B2Publication Date: 2014-03-04
- Inventor: Huilong Zhu , Haizhou Yin , Zhijiong Luo
- Applicant: Huilong Zhu , Haizhou Yin , Zhijiong Luo
- Applicant Address: CN Beijing
- Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee Address: CN Beijing
- Agency: VLP Law Group LLP
- Agent Enshan Hong
- Priority: CN201110033687 20110130
- International Application: PCT/CN2011/072961 WO 20110418
- International Announcement: WO2012/100463 WO 20120802
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.
Public/Granted literature
- US20120264262A1 Method for forming semiconductor structure Public/Granted day:2012-10-18
Information query
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