Invention Grant
- Patent Title: Method and system for model-based design and layout of an integrated circuit
-
Application No.: US13535242Application Date: 2012-06-27
-
Publication No.: US08645887B2Publication Date: 2014-02-04
- Inventor: Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
- Applicant: Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
Public/Granted literature
- US20120272201A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT Public/Granted day:2012-10-25
Information query