Invention Grant
US08645787B2 Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor
有权
用于控制非二进制LDPC码解码器的基本奇偶校验节点的方法,以及对应的基本奇偶校验节点处理器
- Patent Title: Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor
- Patent Title (中): 用于控制非二进制LDPC码解码器的基本奇偶校验节点的方法,以及对应的基本奇偶校验节点处理器
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Application No.: US13319033Application Date: 2010-05-05
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Publication No.: US08645787B2Publication Date: 2014-02-04
- Inventor: Emmanuel Boutillon , Laura Conde-Canencia
- Applicant: Emmanuel Boutillon , Laura Conde-Canencia
- Applicant Address: FR Lorient FR Paris
- Assignee: Universite de Bretagne Sud,Centre National de la Recherche Scientifique-CNRS
- Current Assignee: Universite de Bretagne Sud,Centre National de la Recherche Scientifique-CNRS
- Current Assignee Address: FR Lorient FR Paris
- Agency: Patterson Thuente Pedersen, P.A.
- Priority: FR0952988 20090505
- International Application: PCT/FR2010/050856 WO 20100505
- International Announcement: WO2010/128248 WO 20101111
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/00

Abstract:
A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1, U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm′ elements sorted in said ascending or descending order, nm′ being greater than 1, each element of the output list (Uout) being the result of a computing operation φ between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.
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