A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan testing by way of an external automatic test pattern generator (ATPG) tool. The ATPG tool generates first and second sets of test patterns for module level and chip level scan testing of the integrated circuit. The ATPG tool generates the second set of test patterns by excluding the design faults which have already been targeted during the module level scan testing, from the first set of test patterns and reduces the overall time required for scan testing the integrated circuit.