A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.