Invention Grant
- Patent Title: Dynamic random access memory address line test technique
- Patent Title (中): 动态随机存取存储器地址线测试技术
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Application No.: US13135374Application Date: 2011-07-01
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Publication No.: US08644098B2Publication Date: 2014-02-04
- Inventor: Peiyuan Liu , Henri Girard
- Applicant: Peiyuan Liu , Henri Girard
- Agent Robert D. Shedd; Robert Levy
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C29/00 ; G11C29/56

Abstract:
Verification of the address connections of a memory (14) having multiplexed banks rows and columns commences by selecting a first address location having a bank/row/column value and then writing a pattern to a second location corresponding to the first location where one of the column, row, bank addresses could become stuck high or low. A second pattern gets written to the first location and a comparison occurs between the second pattern and first pattern written to the second location. If the data is the same, then that particular row/column/bank addresses is stuck.
Public/Granted literature
- US20120250438A1 Dynamic random access memory address line test technique Public/Granted day:2012-10-04
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