Invention Grant
- Patent Title: Semiconductor package with through silicon vias and method for making the same
- Patent Title (中): 具有硅通孔的半导体封装及其制造方法
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Application No.: US13311364Application Date: 2011-12-05
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Publication No.: US08643167B2Publication Date: 2014-02-04
- Inventor: Chia-Lin Hung , Jen-Chuan Chen , Hui-Shan Chang , Kuo-Pin Yang
- Applicant: Chia-Lin Hung , Jen-Chuan Chen , Hui-Shan Chang , Kuo-Pin Yang
- Applicant Address: TW
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW
- Agency: Morgan Law Offices, PLC
- Priority: TW100100425A 20110106
- Main IPC: H01L23/04
- IPC: H01L23/04 ; H01L23/34
Abstract:
The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.
Public/Granted literature
- US20120175767A1 SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS AND METHOD FOR MAKING THE SAME Public/Granted day:2012-07-12
Information query
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