Invention Grant
- Patent Title: Logic corruption verification
- Patent Title (中): 逻辑损坏验证
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Application No.: US13290511Application Date: 2011-11-07
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Publication No.: US08527826B2Publication Date: 2013-09-03
- Inventor: Nutan J. P. Kumar , Srinivas V. N. Polisetty
- Applicant: Nutan J. P. Kumar , Srinivas V. N. Polisetty
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Michael J. LeStrange
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A computer-implemented method of verifying logic in a simulation-based behavioral latch model by performing actions including: inserting a value checking module in the behavioral latch model, the value checking module connected to one of a set of latches outside of a scan chain within the behavioral latch model; comparing a value of the one of the set of latches outside of the scan chain with a delta value for the one of the set of latches outside of the scan chain; and providing an error message in response to determining the value and the delta value are distinct.
Public/Granted literature
- US20130117619A1 LOGIC CORRUPTION VERIFICATION Public/Granted day:2013-05-09
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