The present invention provides an information processing device having a CPU which executes an OS and firmware, and a plurality of memory controllers which are connected to the CPU, control writing to and reading from a plurality of memory units, and perform error monitoring, wherein the plurality of memory units each connected to the plurality of memory controllers, the memory controllers sequentially read memory areas of the plurality of memory units connected to the memory controllers, and perform error area monitoring, and the firmware converts addresses recognized by the memory controllers corresponding to the error areas into logical addresses recognized by the OS, and supplies the logical addresses to the OS.