Invention Grant
US08527708B2 Detecting address conflicts in a cache memory system 失效
检测高速缓冲存储器系统中的地址冲突

Detecting address conflicts in a cache memory system
Abstract:
A cache memory providing improved address conflict detection by reference to a set associative array includes a data array that stores memory blocks, a directory of contents of the data array, and a cache controller that controls access to the data array. The cache controller includes an address conflict detection system having a set-associative array configured to store at least tags of memory addresses of in-flight memory access transactions. The address conflict detection system accesses the set-associative array to detect if a target address of an incoming memory access transaction conflicts with that of an in-flight memory access transaction and determines whether to allow the incoming transaction memory access transaction to proceed based upon the detection.
Public/Granted literature
Information query
Patent Agency Ranking
0/0