Invention Grant
- Patent Title: Echo cancellation circuit
- Patent Title (中): 回波消除电路
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Application No.: US13044346Application Date: 2011-03-09
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Publication No.: US08526339B2Publication Date: 2013-09-03
- Inventor: Shinji Nakatsuka , Kazuhiro Oda
- Applicant: Shinji Nakatsuka , Kazuhiro Oda
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Sprinkle IP Law Group
- Priority: JP2010-057922 20100315; JP2010-057923 20100315
- Main IPC: H04B3/20
- IPC: H04B3/20

Abstract:
An echo cancellation circuit in a full duplex two-way communication system comprising: an input/output terminal; a subtractor having a positive and a negative input terminals, in which a first transmission signal is inputted to the negative input terminal as a pseudo echo signal, the first transmission signal is inputted through an output buffer to the positive input terminal as an echo signal, the pseudo echo signal inputted to the negative input terminal is subtracted from the echo signal inputted to the positive input terminal; and a result of the subtraction is outputted; and an echo cancellation error reducing unit having a D/A converter at an input side or an output side of the subtractor.
Public/Granted literature
- US20110222446A1 ECHO CANCELLATION CIRCUIT Public/Granted day:2011-09-15
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