Invention Grant
- Patent Title: Eutectic flow containment in a semiconductor fabrication process
- Patent Title (中): 半导体制造工艺中的共晶流动遏制
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Application No.: US12914859Application Date: 2010-10-28
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Publication No.: US08525316B2Publication Date: 2013-09-03
- Inventor: Lisa H. Karlin , Hemant D. Desai
- Applicant: Lisa H. Karlin , Hemant D. Desai
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Main IPC: H01L23/488
- IPC: H01L23/488

Abstract:
A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.
Public/Granted literature
- US20110042761A1 EUTECTIC FLOW CONTAINMENT IN A SEMICONDUCTOR FABRICATION PROCESS Public/Granted day:2011-02-24
Information query
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