Invention Grant
- Patent Title: Semiconductor fuse with enhanced post-programming resistance
- Patent Title (中): 半导体保险丝具有增强的后编程电阻
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Application No.: US13231194Application Date: 2011-09-13
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Publication No.: US08524567B2Publication Date: 2013-09-03
- Inventor: Andreas Kurz , Maciej Wiatr
- Applicant: Andreas Kurz , Maciej Wiatr
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Dittavong Mori & Steiner, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
Public/Granted literature
- US20130062726A1 SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE Public/Granted day:2013-03-14
Information query
IPC分类: