Invention Grant
US08504969B2 Filler cells for design optimization in a place-and-route system
有权
填充单元用于在路线和路径系统中进行设计优化
- Patent Title: Filler cells for design optimization in a place-and-route system
- Patent Title (中): 填充单元用于在路线和路径系统中进行设计优化
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Application No.: US12961732Application Date: 2010-12-07
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Publication No.: US08504969B2Publication Date: 2013-08-06
- Inventor: Xi-Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
- Applicant: Xi-Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.
Public/Granted literature
- US20110078639A1 FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM Public/Granted day:2011-03-31
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