Invention Grant
- Patent Title: Through-hole layout apparatus that reduces differences in layout density of through-holes
- Patent Title (中): 通孔布局装置,减少了通孔布局密度的差异
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Application No.: US12478834Application Date: 2009-06-05
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Publication No.: US08504964B2Publication Date: 2013-08-06
- Inventor: Hayato Ooishi , Kazuhiko Matsuki
- Applicant: Hayato Ooishi , Kazuhiko Matsuki
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2008-149172 20080606
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A through-hole layout apparatus and method for reducing differences in layout density of through-holes. The through-hole layout apparatus includes an extractor, which extracts an existing through-hole from design data for a semiconductor integrated circuit, a calculator, which calculates a layout density of through-holes in a predetermined region for each through-hole extracted by the extractor, a selector, which selects a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor and a through-hole adder, which determines a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added for each target through-hole selected by the selector.
Public/Granted literature
- US20090307648A1 THROUGH-HOLE LAYOUT APPARATUS THAT REDUCES DIFFERENCES IN LAYOUT DENSITY OF THROUGH-HOLES Public/Granted day:2009-12-10
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