Invention Grant
- Patent Title: Integrated circuit with timing adjustment mechanism
- Patent Title (中): 具有定时调整机制的集成电路
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Application No.: US13067249Application Date: 2011-05-18
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Publication No.: US08504961B2Publication Date: 2013-08-06
- Inventor: Virgile Javerliac
- Applicant: Virgile Javerliac
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An integrated circuit includes processing circuitry that includes a plurality of critical path circuits. These critical path circuits include variable delay circuits which add an additional delay in to a path delay through each of the critical path circuits so as to adjust the path delay to match a target path delay. Variable delay circuit includes a tank capacitor which is charged or discharged to generate a control voltage. This control voltage serves to control a power supply voltage fed to an inverter chain. Variation in the power supply voltage of the inverter chain adjust the propagation speed of a processing signal through the inverter chain and accordingly adjusts the additional delay imposed by the variable delay circuit.
Public/Granted literature
- US20110291731A1 Integrated circuit with timing adjustment mechanism Public/Granted day:2011-12-01
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