Invention Grant
- Patent Title: Memory controller
- Patent Title (中): 内存控制器
-
Application No.: US12120489Application Date: 2008-05-14
-
Publication No.: US08504897B2Publication Date: 2013-08-06
- Inventor: Masayuki Imagawa , Tetsuo Furuichi
- Applicant: Masayuki Imagawa , Tetsuo Furuichi
- Applicant Address: JP Osaka-shi
- Assignee: MegaChips Corporation
- Current Assignee: MegaChips Corporation
- Current Assignee Address: JP Osaka-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-163423 20070621; JP2007-236847 20070912
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.
Public/Granted literature
- US20080320342A1 MEMORY CONTROLLER Public/Granted day:2008-12-25
Information query