Invention Grant
- Patent Title: Column command buffer and latency circuit including the same
- Patent Title (中): 列命令缓冲器和延迟电路包括相同
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Application No.: US12841095Application Date: 2010-07-21
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Publication No.: US08503256B2Publication Date: 2013-08-06
- Inventor: Jae Bum Ko
- Applicant: Jae Bum Ko
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2010-0029070 20100331
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.
Public/Granted literature
- US20110242911A1 COLUMN COMMAND BUFFER AND LATENCY CIRCUIT INCLUDING THE SAME Public/Granted day:2011-10-06
Information query
