Invention Grant
- Patent Title: Non-binary decoder architecture and control signal logic for reduced circuit complexity
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Application No.: US13127878Application Date: 2009-11-04
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Publication No.: US08502563B2Publication Date: 2013-08-06
- Inventor: Matias N. Troccoli
- Applicant: Matias N. Troccoli
- Applicant Address: NO Nesoya
- Assignee: Next Biometrics AS
- Current Assignee: Next Biometrics AS
- Current Assignee Address: NO Nesoya
- Agency: Duane Morris LLP
- International Application: PCT/US2009/063202 WO 20091104
- International Announcement: WO2010/053938 WO 20100514
- Main IPC: H03K19/082
- IPC: H03K19/082
Abstract:
A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log2X inputs for receiving the clock signal inputs.
Public/Granted literature
- US20110221474A1 NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY Public/Granted day:2011-09-15
Information query
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