Invention Grant
US08502355B2 Overlay vernier mask pattern, formation method thereof, semiconductor device including overlay vernier pattern, and formation method thereof
失效
覆盖游标掩模图案及其形成方法，包括覆盖游标图案的半导体器件及其形成方法
- Patent Title: Overlay vernier mask pattern, formation method thereof, semiconductor device including overlay vernier pattern, and formation method thereof
- Patent Title (中): 覆盖游标掩模图案及其形成方法，包括覆盖游标图案的半导体器件及其形成方法
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Application No.: US13315742Application Date: 2011-12-09
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Publication No.: US08502355B2Publication Date: 2013-08-06
- Inventor: Joon Seuk Lee
- Applicant: Joon Seuk Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2010-0125808 20101209
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and a second overlay vernier mask pattern aligned on the first overlay vernier mask pattern and the layer to be etched, and having an opening for exposing the second opening while exposing a portion of the layer to be etched in the first area.
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