Invention Grant
US08502307B2 Vertical power semiconductor carrier having laterally isolated circuit areas
有权
具有侧向隔离电路区域的垂直功率半导体载体
- Patent Title: Vertical power semiconductor carrier having laterally isolated circuit areas
- Patent Title (中): 具有侧向隔离电路区域的垂直功率半导体载体
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Application No.: US12953682Application Date: 2010-11-24
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Publication No.: US08502307B2Publication Date: 2013-08-06
- Inventor: Christoph Kadow , Thorsten Meyer
- Applicant: Christoph Kadow , Thorsten Meyer
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side. A conductive pathway extends through the semiconductor carrier from the first side to the second side, and is electrically insulated from the semiconductor carrier surrounding the conductive pathway. At least one of the first circuit elements is electrically coupled to a contact area at the first side via the conductive pathway.
Public/Granted literature
- US20120126318A1 Integrated Circuit Including Field Effect Transistor Public/Granted day:2012-05-24
Information query
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