Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.