Invention Grant
US08479085B2 Memory system with error correction decoder architecture having reduced latency and increased throughput
有权
具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量
- Patent Title: Memory system with error correction decoder architecture having reduced latency and increased throughput
- Patent Title (中): 具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量
-
Application No.: US12191458Application Date: 2008-08-14
-
Publication No.: US08479085B2Publication Date: 2013-07-02
- Inventor: Nam Phil Jo , Jun Jin Kong , Chan Ho Yoon , Dong Hyuk Chae , Kyoung Lae Cho
- Applicant: Nam Phil Jo , Jun Jin Kong , Chan Ho Yoon , Dong Hyuk Chae , Kyoung Lae Cho
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2007-0082549 20070817
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
Public/Granted literature
- US20090070656A1 MEMORY SYSTEM WITH ERROR CORRECTION DECODER ARCHITECTURE HAVING REDUCED LATENCY AND INCREASED THROUGHPUT Public/Granted day:2009-03-12
Information query