Invention Grant
- Patent Title: Failure analyzing device and failure analyzing method
- Patent Title (中): 故障分析装置及故障分析方法
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Application No.: US12966687Application Date: 2010-12-13
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Publication No.: US08479063B2Publication Date: 2013-07-02
- Inventor: Yoshikazu Iizuka
- Applicant: Yoshikazu Iizuka
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2010-175400 20100804
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
According to one embodiment, a failure analyzing device includes a classifying unit that classifies a failure type in a fail bit map corresponding to each layer, a storage unit that stores a rule to combine failed cells of different layers, and a determining unit that groups a classification result matched with the rule among classification results based on the classifying unit. The rule includes a base point failure, an association failure becoming a combination object of the base point failure, a combination condition defining a relationship between the base point failure and the association failure, and a combination failure name. The determining unit extracts the base point failure from the classification result of one layer, extracts the association failure matched with the combination condition from the classification results of the other layers, groups the extracted base point failure and association failure, and provides the combination failure name.
Public/Granted literature
- US20120036405A1 FAILURE ANALYZING DEVICE AND FAILURE ANALYZING METHOD Public/Granted day:2012-02-09
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