In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly.