Invention Grant
- Patent Title: Semiconductor device conductive pattern structures including dummy conductive patterns
- Patent Title (中): 包括虚拟导电图案的半导体器件导电图案结构
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Application No.: US13237514Application Date: 2011-09-20
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Publication No.: US08476763B2Publication Date: 2013-07-02
- Inventor: Hei-Seung Kim , In-Sun Park , Gil-Heyun Choi , Ji-Soon Park , Jong-Myeong Lee , Jong-Won Hong
- Applicant: Hei-Seung Kim , In-Sun Park , Gil-Heyun Choi , Ji-Soon Park , Jong-Myeong Lee , Jong-Won Hong
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2011-0009342 20110131
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/4763 ; H01L27/10 ; H01L21/3205 ; H01L21/768 ; G06F17/50

Abstract:
Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
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