Invention Grant
US08476718B2 Semiconductor device including a gate insulating film having a metal oxide layer having trap levels
有权
半导体器件包括具有陷阱电平的金属氧化物层的栅极绝缘膜
- Patent Title: Semiconductor device including a gate insulating film having a metal oxide layer having trap levels
- Patent Title (中): 半导体器件包括具有陷阱电平的金属氧化物层的栅极绝缘膜
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Application No.: US12710851Application Date: 2010-02-23
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Publication No.: US08476718B2Publication Date: 2013-07-02
- Inventor: Izumi Hirano , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
- Applicant: Izumi Hirano , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-074427 20090325
- Main IPC: H01L21/02
- IPC: H01L21/02

Abstract:
A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm−3 to 2.96×1020 cm−3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.
Public/Granted literature
- US20100244157A1 SEMICONDUCTOR DEVICE Public/Granted day:2010-09-30
Information query
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