Invention Grant
US08476630B2 Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon
有权
将焊盘和一个或多个互连层添加到晶片的钝化顶层的方法包括与其上的集成电路焊盘的至少一部分的连接
- Patent Title: Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon
- Patent Title (中): 将焊盘和一个或多个互连层添加到晶片的钝化顶层的方法包括与其上的集成电路焊盘的至少一部分的连接
-
Application No.: US13314327Application Date: 2011-12-08
-
Publication No.: US08476630B2Publication Date: 2013-07-02
- Inventor: Morgan T. Johnson
- Applicant: Morgan T. Johnson
- Applicant Address: US OR Beaverton
- Assignee: Advanced Inquiry Systems, Inc.
- Current Assignee: Advanced Inquiry Systems, Inc.
- Current Assignee Address: US OR Beaverton
- Agency: Perkins Coie LLP
- Main IPC: H01L29/04
- IPC: H01L29/04
Abstract:
A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.
Public/Granted literature
Information query
IPC分类:
