Invention Grant
- Patent Title: Reducing wafer distortion through a low CTE layer
- Patent Title (中): 通过低CTE层减少晶片失真
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Application No.: US12959984Application Date: 2010-12-03
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Publication No.: US08476146B2Publication Date: 2013-07-02
- Inventor: Chi-Ming Chen , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
- Applicant: Chi-Ming Chen , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/76 ; H01L21/762

Abstract:
Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.
Public/Granted literature
- US20120138945A1 REDUCING WAFER DISTORTION THROUGH A LOW CTE LAYER Public/Granted day:2012-06-07
Information query
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