Invention Grant
- Patent Title: Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
- Patent Title (中): 具有垂直互连的集成电路封装系统及其制造方法
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Application No.: US13118310Application Date: 2011-05-27
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Publication No.: US08476135B2Publication Date: 2013-07-02
- Inventor: JinGwan Kim , Hyunil Bae
- Applicant: JinGwan Kim , Hyunil Bae
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent I-Chang John Yang
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side.
Public/Granted literature
- US20120299168A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2012-11-29
Information query
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