Invention Grant
- Patent Title: Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
- Patent Title (中): 形成三维垂直取向的集成电容器的半导体器件和方法
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Application No.: US13421770Application Date: 2012-03-15
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Publication No.: US08476120B2Publication Date: 2013-07-02
- Inventor: Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow
- Applicant: Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group:Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/20 ; H01L21/02 ; H01L23/02 ; H01L23/28

Abstract:
A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.
Public/Granted literature
- US20120168963A1 Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors Public/Granted day:2012-07-05
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