The present invention provides a phase and/or frequency detector, a PLL and an operation method for the PLL. The phase and/or frequency detector comprises two flip-flops, a logic gate, a control circuit and a delay circuit. The clock-input terminals of the two flip-flops receive a reference signal and a frequency-divided signal respectively. The logic gate receives signals outputted from the data-output terminals of the two flip-flops. The control circuit is configured for generating a corresponding delay control signal according to an oscillating frequency of an oscillating signal outputted from the PLL. The delay circuit is configured for altering a prolonged period according to the delay control signal to output a reset signal to the reset terminals of the two flip-flops.