Invention Grant
- Patent Title: Determining intra-die wirebond pad placement locations in integrated circuit
- Patent Title (中): 确定集成电路中的管芯内焊盘放置位置
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Application No.: US13032059Application Date: 2011-02-22
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Publication No.: US08448118B2Publication Date: 2013-05-21
- Inventor: Richard S. Graf , Haruo Itoh , Wai Ling Chung-Maloney
- Applicant: Richard S. Graf , Haruo Itoh , Wai Ling Chung-Maloney
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Richard M. Kotulak
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (IR) drop across the first region and the second region; comparing the IR drops across the regions; and in response to the IR drops being substantially unequal, moving the dividing band, determining new IR drops across the regions, and comparing the new IR drops until the IR drops are substantially equal. The dividing band may provide desired locations for intra-die wirebond pads.
Public/Granted literature
- US20120216164A1 DETERMINING INTRA-DIE WIREBOND PAD PLACEMENT LOCATIONS IN INTEGRATED CIRCUIT Public/Granted day:2012-08-23
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