The described embodiments provide a processor for generating a result vector with subtracted or mathematically divided values from a first input vector. During operation, the processor receives the first input vector, a second input vector, and a control vector, and optionally receives a predicate vector. The processor then records a value from an element at a key element position in the second input vector into a base value. Next, the processor generates a result vector. When generating the result vector, for each active element in the result vector to the right of the key element position, the processor is configured to set the element in the result vector equal to the base value minus a total of the values in each relevant element of the first input vector or to set the element in the result vector equal to the result of dividing the base value by a value in each relevant element of the first input vector, wherein the relevant elements include relevant elements from an element at the key element position to and including a predetermined element in the first input vector.