Invention Grant
US08447796B2 Apparatus with a vector generation unit and encoder for receiving first and second inputs to generate at least significant zero (LSZ)
失效
具有矢量生成单元和编码器的装置，用于接收第一和第二输入以产生至少显着的零（LSZ）
- Patent Title: Apparatus with a vector generation unit and encoder for receiving first and second inputs to generate at least significant zero (LSZ)
- Patent Title (中): 具有矢量生成单元和编码器的装置，用于接收第一和第二输入以产生至少显着的零（LSZ）
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Application No.: US12313841Application Date: 2008-11-25
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Publication No.: US08447796B2Publication Date: 2013-05-21
- Inventor: Vinodh Gopal
- Applicant: Vinodh Gopal
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Troper, Pruner & Hu, P.C.
- Main IPC: H04L27/00
- IPC: H04L27/00
Abstract:
In one embodiment, the present invention includes a method for receiving a first and second inputs, calculating a sum/difference of the first and second inputs in parallel with determining a least significant zero (LSZ) vector using the first and second inputs, and determining a shift value based on the LSZ vector, where the shift value is used to perform a shift operation on the sum/difference. Other embodiments are described and claimed.
Public/Granted literature
- US20100128812A1 Efficiently computing a divisor Public/Granted day:2010-05-27
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