Invention Grant
- Patent Title: Distortion compensation circuit and a distortion compensation method
- Patent Title (中): 失真补偿电路和失真补偿方法
-
Application No.: US12991393Application Date: 2009-05-22
-
Publication No.: US08446980B2Publication Date: 2013-05-21
- Inventor: Junya Ashita
- Applicant: Junya Ashita
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2008-138817 20080528
- International Application: PCT/JP2009/059830 WO 20090522
- International Announcement: WO2009/145283 WO 20091203
- Main IPC: H04K1/02
- IPC: H04K1/02
Abstract:
A distortion compensation circuit is provided with an input level limitation unit that limits signal level of an input signal and outputs a signal before distortion compensation, a distortion compensation unit that performs distortion compensation processing to the signal before distortion compensation and outputs a signal after distortion compensation, an distortion compensation coefficient calculation unit that calculates a coefficient for compensating distortion of the output signal of an amplifier as a distortion compensation coefficient, a storage unit that stores the distortion compensation coefficient and a limit value calculation unit that calculates signal level of the signal before distortion compensation.
Public/Granted literature
- US20110064155A1 DISTORTION COMPENSATION CIRCUIT AND A DISTORTION COMPENSATION METHOD Public/Granted day:2011-03-17
Information query
