According to one embodiment, a NAND nonvolatile semiconductor memory device comprises memory cell transistors and a write circuit. The memory cell transistors are arranged in a matrix in a column direction and in a row direction. Each of the memory cell transistors comprises a charge accumulation layer and a control gate electrode configured to control the charge accumulation state of the charge accumulation layer. The write circuit carries out write on the memory cell transistors. The memory cell transistors arranged in the same line include first memory cell transistors and second memory cell transistors that are smaller than the first memory cell transistors in the column direction. The write circuit carries out write on a predetermined first memory cell transistor and then on another first memory cell transistor. After the write on the another first memory cell transistor, the write circuit carries out write on the second memory cell transistor.