According to one embodiment, the data transfer circuit outputs n bits for each N columns (n≧2) in the pixel array among digital data of a predetermined number of bits digitally converted in accordance with the column selection signal which collectively and sequentially selects N columns (N≧2) in the pixel array by using one data line. One data line is commonly and correspondingly connected to one differential input terminals of 2n−1 differential amplifier circuits arranged in the column direction in an input stage of the signal processing circuit, and corresponding one of 2n−1 reference voltage lines is connected to the other differential input terminals.