Invention Grant
US08446193B2 Apparatus and method to hold PLL output frequency when input clock is lost
有权
输入时钟丢失时保持PLL输出频率的装置和方法
- Patent Title: Apparatus and method to hold PLL output frequency when input clock is lost
- Patent Title (中): 输入时钟丢失时保持PLL输出频率的装置和方法
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Application No.: US13099253Application Date: 2011-05-02
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Publication No.: US08446193B2Publication Date: 2013-05-21
- Inventor: Ben-yong Zhang , Tom Christiansen , Christopher Andrew Schell
- Applicant: Ben-yong Zhang , Tom Christiansen , Christopher Andrew Schell
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Andrew S. Viger; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.
Public/Granted literature
- US20120280735A1 APPARATUS AND METHOD TO HOLD PLL OUTPUT FREQUENCY WHEN INPUT CLOCK IS LOST Public/Granted day:2012-11-08
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