Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
-
Application No.: US12801498Application Date: 2010-06-11
-
Publication No.: US08446192B2Publication Date: 2013-05-21
- Inventor: Hiroki Kimura
- Applicant: Hiroki Kimura
- Applicant Address: JP Tokyo
- Assignee: Nihon Dempa Kogyo Co., Ltd
- Current Assignee: Nihon Dempa Kogyo Co., Ltd
- Current Assignee Address: JP Tokyo
- Agency: Jacobson Holman PLLC
- Priority: JPP.2009-141116 20090612; JPP.2010-081506 20100331
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit 3 provides a frequency division ratio table 32 where frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from the table 32, the frequency division ratio corresponding to the temperature detected by the temperature sensor 31 and an input channel number, to set the frequency division ratio in a PLL IC 2 and to set the channel number and the frequency division ratio in a DDS circuit 4. The DDS circuit 4 calculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency.
Public/Granted literature
- US20100315137A1 PLL circuit Public/Granted day:2010-12-16
Information query