Invention Grant
US08446011B2 Devices and memory arrays including bit lines and bit line contacts
有权
器件和存储器阵列，包括位线和位线触点
- Patent Title: Devices and memory arrays including bit lines and bit line contacts
- Patent Title (中): 器件和存储器阵列，包括位线和位线触点
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Application No.: US13243510Application Date: 2011-09-23
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Publication No.: US08446011B2Publication Date: 2013-05-21
- Inventor: Seiichi Aritome
- Applicant: Seiichi Aritome
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.
Public/Granted literature
- US20120104463A1 DEVICES AND MEMORY ARRAYS INCLUDING BIT LINES AND BIT LINE CONTACTS Public/Granted day:2012-05-03
Information query
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