Invention Grant
- Patent Title: Parallel scan paths with stimulus and header data circuitry
- Patent Title (中): 具有刺激和标题数据电路的并行扫描路径
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Application No.: US13595297Application Date: 2012-08-27
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Publication No.: US08445908B2Publication Date: 2013-05-21
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H01L29/10
- IPC: H01L29/10 ; G01R31/28
Abstract:
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
Public/Granted literature
- US20120324304A1 SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS Public/Granted day:2012-12-20
Information query
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