Invention Grant
US08438526B2 Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions
有权
通过设计规则限制最小化CMOS工艺中晶体管和模拟元件变化的方法
- Patent Title: Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions
- Patent Title (中): 通过设计规则限制最小化CMOS工艺中晶体管和模拟元件变化的方法
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Application No.: US12889116Application Date: 2010-09-23
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Publication No.: US08438526B2Publication Date: 2013-05-07
- Inventor: Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
- Applicant: Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Alan A. R. Cooper; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455
Abstract:
Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.
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